原始文献 / 论坛帖 / Auto-detect for 128-bit 4-way SSE2
Auto-detect for 128-bit 4-way SSE2
Bitcointalk · 2010-09-09 01:04:05 UTC
SVN rev 150 有些代码，尝试自动检测是否用 4-way SSE2。我们需要这个，因为它只在某些有 128 位 SSE2 的较新 CPU 上更快，64 位 SSE2 的不行。
它用 CPUID 指令获取 CPU 品牌、家族、型号和步进。这是容易的部分。难的是知道拿型号怎么办。我找不到 CPU 家族、型号、步进编号表，只能依据看到的各种零散报告。
最后是这样的：
Code: // We need Intel Nehalem or AMD K10 or better for 128bit SSE2
// Nehalem = i3/i5/i7 and some Xeon
// K10 = Opterons with 4 or more cores, Phenom, Phenom II, Athlon II
// Intel Core i5 family 6, model 26 or 30
// Intel Core i7 family 6, model 26 or 30
// Intel Core i3 family 6, model 37
// AMD Phenom family 16, model 10
bool fUseSSE2 = ((fIntel && nFamily * 10000 + nModel >= 60026) ||
(fAMD && nFamily * 10000 + nModel >= 160010));
我在 AMD CPU 上看到一些零散的不一致的型号，所以不确定这能不能覆盖所有有能力的 AMD。
如果错了，你还可以用 -4way 或 -4way=0 覆盖。
它把发现的东西打印到 debug.log。搜 CPUID。
只在用 GCC 构建时启用。
英文原文
SVN rev 150 has some code to try to auto-detect whether to use 4-way SSE2. We need this because it's only faster on certain newer CPUs that have 128-bit SSE2 and not ones with 64-bit SSE2.
It uses the CPUID instruction to get the CPU brand, family, model number and stepping. That's the easy part. Knowing what to do with the model number is the hard part. I was not able to find any table of family, model and stepping numbers for CPUs. I had to go by various random reports I saw.
Here's what I ended up with:
Code: // We need Intel Nehalem or AMD K10 or better for 128bit SSE2
// Nehalem = i3/i5/i7 and some Xeon
// K10 = Opterons with 4 or more cores, Phenom, Phenom II, Athlon II
// Intel Core i5 family 6, model 26 or 30
// Intel Core i7 family 6, model 26 or 30
// Intel Core i3 family 6, model 37
// AMD Phenom family 16, model 10
bool fUseSSE2 = ((fIntel && nFamily * 10000 + nModel >= 60026) ||
(fAMD && nFamily * 10000 + nModel >= 160010));
I saw some sporadic inconsistent model numbers for AMD CPUs, so I'm not sure if this will catch all capable AMDs.
If it's wrong, you can still override it with -4way or -4way=0.
It prints what it finds in debug.log. Search on CPUID.
This is only enabled if built with GCC.